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1
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10.0k
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1
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Write VHDL code for 3:8 decoder with active low truth table
digital system design updated 2.1 years ago by sagarkolekar ★ 11k
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1
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9.4k
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1
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Design a VHDL Code for 4-Bit Down-Counter.
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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9.3k
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1
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VHDL code for Sequence detector (101) using Mealy state machine.
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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8.9k
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1
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Implement the following Boolean function with 8: multiplexer F(A,B,C,D)=?m(0,3,5,6,8,9,10,12,14).
digital system design updated 3.0 years ago by teamques10 ★ 65k
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1
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8.8k
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1
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Explain what entity in VHDL is?
digital system design updated 2.1 years ago by pedsangini276 • 4.8k
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1
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7.9k
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1
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Explain Mealy machine and Moore machine
digital system design updated 4.6 years ago by abhishektiwari1 • 100
2
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1
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7.3k
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1
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Explain CPLD and FPGA
digital system design updated 4.6 years ago by abhishektiwari1 • 100
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1
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6.7k
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1
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Implement the Boolean function using 8:1 multiplexer
digital system design updated 4.6 years ago by abhishektiwari1 • 100
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0
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6.7k
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0
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(Duplicate) Modelling styles in VHDL
digital system design updated 2.1 years ago by teamques10 ★ 65k
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1
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6.7k
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1
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Design a 4 bit Bidirectional Universal MSI Shift Register
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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6.2k
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1
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Design a VHDL Code for Half Subtractor.
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
1
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1
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6.1k
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1
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Explain the Johnson's Counter. Design for initial state 0110. From initial state explain and draw all possible states.
digital system design updated 4.6 years ago by abhishektiwari1 • 100
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1
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5.8k
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1
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Design a VHDL Code for 4-Bit Up-Counter.
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
0
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1
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5.6k
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1
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Explain Master Slave JK Flip Flop
digital system design updated 4.6 years ago by abhishektiwari1 • 100
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1
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5.3k
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1
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VHDL code for Sequence detector (101) using Moore state machine.
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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5.0k
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1
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What is shift register? Explain any one type of shift register. Give its applications OR What are shift registers? How are they classified? Explain working of any one type of shift register
digital system design updated 4.6 years ago by abhishektiwari1 • 100
0
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1
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4.6k
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1
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Design a VHDL Code for 4:2 Encoders.
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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4.4k
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1
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Write a Short Note on Entity & Architecture Declaration of VHDL
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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4.3k
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1
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Write a short note on Moore & Mealy Models
digital system design updated 2.2 years ago by yashbeer ★ 11k
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1
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4.3k
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1
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Design a VHDL Code for BCD to 7 Segment Decoder.
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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4.3k
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1
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Design a VHDL Code for 2:4 Decoders.
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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4.1k
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1
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Perform the following operation using 2's compliment
digital system design updated 4.6 years ago by abhishektiwari1 • 100
2
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1
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4.1k
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1
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Express F in SOP and POS form
digital system design updated 4.6 years ago by abhishektiwari1 • 100
0
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1
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3.8k
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1
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Write a note on Magnitude Comparator
digital system design updated 4.6 years ago by abhishektiwari1 • 100
0
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1
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3.6k
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1
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Design Magnitude Comparator using PLAs
digital system design updated 2.3 years ago by pedsangini276 • 4.8k
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